As the design community is developing further in areas like common design language
(VHDL, Verilog), availability of complete design blocks from different companies (Fabless
Design Houses) and reuse of all these blocks in different SOC-designs, there is a major
improvement in time-to-market possible.

The challenge will be to develop test tools (STIL, virtual test, BIST, …) and establish an
infrastructure in order to cope with the market needs.

This allows major improvements in the following fields:

• Design for testability (DFT)
• Design for manufacturability (DFM)
• Distribution of test intelligence (IC, load board, ATE, external instruments)

In order to get a common understanding of needed tools (HW + SW), even a broader
range of players (e.g. EDA providers, ATE and IC manufacturers, fabless design houses,
OEMs, Universities) have to work more closely together.

 

One of the most important subject is the development of a tester independent object
oriented language (e.g. STIL, C++, JAVA). This would allow to develop reusable test
blocks, similar to the design blocks already established from the design community (LEGO-
principal).

Reusable test blocks will contribute to an improved time-to-market, reduces test costs
to appr. 10% of the overall manufacturing costs, gives maximum flexibility for ATE use
and selection, better balancing of tester capacity due to easier transfer of programs to
different ATEs and is an appropriate answer to the shortage of qualified test engineers.